CXL Memory
▶ See it in 3D The Memory Stack region
A newer kind of plumbing that lets many servers share one big pool of memory instead of each hoarding its own. Still early, but it's where merchant chip firms like Astera Labs are starting to make real money.
What it is
Compute Express Link memory expanders attach over the PCIe physical layer with cache coherence — and can be pooled and shared across many hosts. The escape valve when HBM + DDR run out.
The business
The connectivity layer is where merchant silicon makes real money: Astera Labs (controllers, switches), Marvell, Rambus + Montage (controllers), Microchip. Adoption is early but Azure shipped the first production cloud CXL in 2025. Open the CXL region for the full fabric.
Bottleneck severity
Not scarce hardware — scarce silicon and standards: the DRAM inside is commodity, but the controllers and switches that make it poolable come from a handful of design houses (Astera, Montage, Rambus, Microchip), and adoption is gated on each CPU generation actually supporting it.
Who makes it
Astera LabsALAB
The only large-cap pure-play on AI connectivity — Aries retimers, Leo CXL controllers, Scorpio fabric switches. Q2 2026 revenue $392M (+104% YoY) as Scorpio X entered volume; Q3 guided $540–560M. Building NVLink Fusion hybrid racks for 2027. Risk: one customer is most of revenue.
MarvellMRVL
~70% optical-DSP share + custom AI silicon + Celestial AI photonic memory fabric ($3.25B). Most complete optical stack in public equities.
RambusRMBS
Memory-interface IP + chips (CXL, MRDIMM, PCIe). Licensing royalties scale with every DDR5/CXL device.
Montage Tech688008.SH
CXL memory controllers + DDR5 RCD/MRDIMM buffers. China's CXL silicon play.
MicrochipMCHP
Broad-line PCIe/CXL retimers — lower ASP, broader base than Astera. A diversified way to play connectivity content growth.
MicronMU
#3 HBM, the only US-HQ DRAM maker. Qualified on Rubin HBM4; sold out through 2027 and meeting only ~50–65% of what customers ask for. New Idaho capacity doesn't land until 2027–28 — so the squeeze is structural, not seasonal.
Metrics that move this layer
- Connectivity $/GPUcontent per accelerator rising with PCIe gen
- CXL design winscontroller sockets at hyperscalers
- Astera revenuethe pure-play tape on AI connectivity