38 names, grouped by where they sit in the chain. Each one lists what it makes, the metrics to watch, and every file in the atlas it appears in.
Data as of 13 September 2026

#1 HBM maker (~62% share). Qualified HBM4 at NVIDIA first and holds an estimated 60–70% of Rubin's HBM4 allocation, with a TSMC-made logic base die. Sold out through 2027; its CEO calls 2027 potentially the tightest supply year the industry has seen. The bellwether of the whole cycle.
#2 in HBM. Began HBM4 mass production in Feb 2026 and is qualified at NVIDIA — with an in-house 4nm base die, the one turnkey memory+logic+packaging offer. P5 Pyeongtaek pulled forward to late 2027; ~$73B cumulative capex through 2026.
#3 HBM, the only US-HQ DRAM maker. Qualified on Rubin HBM4; sold out through 2027 and meeting only ~50–65% of what customers ask for. New Idaho capacity doesn't land until 2027–28 — so the squeeze is structural, not seasonal.
China's only scaled DRAM maker: ~10% of global DRAM revenue in Q2 2026, ~300k wafers/month heading for 350k, and a 466% first-day pop on its July 2026 STAR listing. But its IPO capex names no HBM line; HBM3 is a 2026–27 target and HBM3E not before 2027 — years behind on the part AI actually needs.

Makes the GPU die AND the CoWoS packaging that bonds HBM to it — and now the logic base die under SK Hynix's HBM4 too. CoWoS is heading for ~130k wafers/month by end-2026 and is still sold out into 2027 (NVIDIA alone holds ~60%); it is farming 240–270k wafers/year of front-end steps out to Amkor and SPIL. A Taiwan disruption stops the whole stack.
Hybrid-bonding tool leader — the technique HBM4 / future stacking needs. Tiny float, huge optionality.

Monopoly on EUV lithography — every leading-edge logic + DRAM die needs it. Ultimate chokepoint.
Etch & deposition tools for HBM's through-silicon vias. HBM tool revenue +50% YoY — equipment ordered today = chips in 12–24 months.
Near-monopoly on wafer dicing & grinding — every advanced chip is thinned and cut on Disco tools. A quiet utilization barometer.
Process control & inspection — finds defects in HBM stacks and advanced packages. Yield gating as stacks go 12-Hi+.
World's largest OSAT. Takes TSMC's CoWoS overflow (SPIL ~60–80k wafers in 2026) and expects advanced-packaging sales to double — a relief valve for the bottleneck, not a substitute at the leading edge.
#2 OSAT (Korea, Vietnam, Arizona). Now the biggest CoWoS outsourcing partner — ~180–190k wafers in 2026, plus ~80k wafers NVIDIA engaged directly. Licensed Intel EMIB; the US-footprint packaging hedge.

Yes — the food company. Invented ABF, the insulating film inside every high-end chip substrate. ~95% of the market, running flat out (~2M m²/month), a new pricing system from Q3 2026 up to +30%, and supply to China cut ~30% to serve everyone else. The quietest monopoly in AI.
~35% of high-end FC-BGA substrates — the board every GPU/CPU package rides on. ¥500B FY2026–28 build-out, but mass production only from FY2027, so the substrate shortage stands through 2026. AI-substrate load index: 1.8× 2024 in 2026, 2.5× by 2028.
World #1 silicon wafers + photoresist. Japan's quiet grip on materials.

The only large-cap pure-play on AI connectivity — Aries retimers, Leo CXL controllers, Scorpio fabric switches. Q2 2026 revenue $392M (+104% YoY) as Scorpio X entered volume; Q3 guided $540–560M. Building NVLink Fusion hybrid racks for 2027. Risk: one customer is most of revenue.
~70% optical-DSP share + custom AI silicon + Celestial AI photonic memory fabric ($3.25B). Most complete optical stack in public equities.
Tomahawk switching + CPO (Davisson 102.4 Tbps) + custom XPUs for hyperscalers. Anchor of the UALink/merchant-silicon camp.
CXL memory controllers + DDR5 RCD/MRDIMM buffers. China's CXL silicon play.
Memory-interface IP + chips (CXL, MRDIMM, PCIe). Licensing royalties scale with every DDR5/CXL device.
Broad-line PCIe/CXL retimers — lower ASP, broader base than Astera. A diversified way to play connectivity content growth.
~25% transceiver share + vertically integrated InP lasers, with all EML capacity locked under long-term agreements through 2027. NVIDIA invested $2B (Mar 2026) explicitly to expand indium-phosphide capacity and pre-allocate it.
The only vendor shipping 200G/lane EML lasers at volume — the exact part 1.6T optics needs — with all EML capacity under long-term agreements through 2027. NVIDIA invested $2B (Mar 2026) to lock it. Purest laser-chokepoint play.
Contract assembler for Coherent, Lumentum, Ciena. The cleanest pluggable-demand barometer — and Thailand is now where InnoLight and Eoptolink build US-bound 1.6T volume too.
World's largest transceiver maker: ~35% of global 800G share, Q1 2026 revenue +207% YoY on the 1.6T ramp; ~60% of NVIDIA's 800G volume with Eoptolink. Depends on US DSPs + JP/US lasers; Thailand plants dodge tariffs.
#2 transceiver maker globally (overtook Coherent in 2025; revenue +189%). Cost-performance leader; Thailand Phase II live for US-bound 1.6T. Same DSP-and-laser dependency as InnoLight.
Coherent long-haul transport (WaveLogic) — the pipes between data centers. Indirect AI beneficiary via data-center interconnect, not intra-cluster optics.
InP/CW lasers, fiber, connectors. Stock +85% in 2025 on laser tightness. Japan's component grip.
Optical fiber + connectors for the AI backbone and CPO fiber arrays.
In-package optical I/O chiplets (TeraPHY). $3.75B Series E; NVIDIA/AMD/Intel backed. IPO signaled.
Passage photonic interposer (114 Tbps). $4.4B valuation; T. Rowe / Google / HPE backed.
Photonic Fabric for optical memory disaggregation. Acquired by Marvell for $3.25B — the valuation anchor.
Buys the most HBM, NVLink and optics on earth and pre-buys supply to lock rivals out: ~60% of CoWoS, $2B each into Coherent and Lumentum (Mar 2026), $2B into Marvell. B300 (288 GB HBM3E) is the shipping reference GPU; Rubin (288 GB HBM4, 22 TB/s) samples Q4 2026, volume Q1 2027.
MI-series GPUs with leading HBM capacity; the anchor of UALink. Zen 6 EPYC "Venice" launched July 2026 with roughly a year before Intel answers; MI400 carries the first UALink production silicon (H2 2026).
Originated CXL; Xeon is the CPU host for CXL memory. Diamond Rapids (18A-P, 256 P-cores, PCIe 6) has slipped to 2027 — handing AMD's Venice a year uncontested. Foundry + photonics IP.
China's leading logic foundry; fabs Huawei's Ascend on 7nm-class DUV multi-patterning with no EUV. Held near 7nm through 2026, which caps every domestic accelerator's performance per die.
Ascend AI accelerators. Roadmap: 910C (2025) → 950PR/950DT (2026) → 960 (2027) → 970 (2028). From the 950 series it uses in-house HBM: HiBL 1.0 (128 GB, 1.6 TB/s) and HiZQ 2.0 (144 GB, 4 TB/s). Today's 910C still runs on stockpiled Samsung/SK Hynix HBM2E. HBM supply, not compute, gates its volume.
Deposition/etch + packaging tools used across HBM TSV and advanced packaging.