CXL Memory Module
▶ See it in 3D The CXL Fabric region
A plug-in box of memory the computer treats as extra (slightly slower) RAM that machines can share. For memory makers it's just a higher-margin version of the same chips; the real brains — and the real margin — is the little controller, made by Astera, Montage, and Rambus.
What it is
A box of DDR5 behind a CXL controller that the CPU sees as a slower, poolable tier of memory. Samsung CMM-D, Micron and SK Hynix ship the modules; the controller silicon is where the value sits.
The business
For the memory makers this is an ASP premium on the same DRAM die. The real margin is the controller: Astera (Leo), Montage, and Rambus IP underneath. Adoption is early — Azure shipped the first production cloud CXL in 2025; the pooling revolution is ~12–18 months ahead of deployments.
Bottleneck severity
The DRAM inside is commodity — the pinch is the controller chip that fronts it (Astera Leo, Montage, Rambus IP). Few firms ship it, and every module pays them.
Who makes it
Samsung005930.KS
#2 in HBM. Began HBM4 mass production in Feb 2026 and is qualified at NVIDIA — with an in-house 4nm base die, the one turnkey memory+logic+packaging offer. P5 Pyeongtaek pulled forward to late 2027; ~$73B cumulative capex through 2026.
MicronMU
#3 HBM, the only US-HQ DRAM maker. Qualified on Rubin HBM4; sold out through 2027 and meeting only ~50–65% of what customers ask for. New Idaho capacity doesn't land until 2027–28 — so the squeeze is structural, not seasonal.
SK Hynix000660.KS
#1 HBM maker (~62% share). Qualified HBM4 at NVIDIA first and holds an estimated 60–70% of Rubin's HBM4 allocation, with a TSMC-made logic base die. Sold out through 2027; its CEO calls 2027 potentially the tightest supply year the industry has seen. The bellwether of the whole cycle.
Astera LabsALAB
The only large-cap pure-play on AI connectivity — Aries retimers, Leo CXL controllers, Scorpio fabric switches. Q2 2026 revenue $392M (+104% YoY) as Scorpio X entered volume; Q3 guided $540–560M. Building NVLink Fusion hybrid racks for 2027. Risk: one customer is most of revenue.
Montage Tech688008.SH
CXL memory controllers + DDR5 RCD/MRDIMM buffers. China's CXL silicon play.
RambusRMBS
Memory-interface IP + chips (CXL, MRDIMM, PCIe). Licensing royalties scale with every DDR5/CXL device.
Metrics that move this layer
- CXL design winscontroller sockets at hyperscalers
- MRDIMM vs CXLcompeting expansion paths
- Rambus royaltiesevery DDR5/CXL module pays IP